The present invention relates to a method of forming shallow diffusion layers in a semiconductor substrate in the vicinity of a gate electrode in a MOS field effect transistor.
As the scaling down of the MOS field effect transistors are required, the problems with short channel effects are raised. In order to suppress the short channel effects, it is necessary to suppress a space charge region from extending under a gate electrode. In order to suppress the space charge region from extending under the gate electrode, it is required that source/drain diffusion layers are formed as shallow as possible.
In order to form shallow source/drain diffusion layers, it is necessary to settle the problems as follows. The first problem is that boron ion is likely to be implanted deeply into a silicon substrate due to channeling. The second problem is a rate-increased thermal diffusion of boron during a heat treatment to the silicon substrate.
In order to solve the above problems, it was proposed that Si or B ion be previously implanted into source/drain regions to make the surface of the silicon substrate amorphous to suppress channeling from appearing in the subsequent ion-implantation of B or BF.sub.2 to form p-type diffusion layers. This technique is disclosed, for example, the Japanese laid-open patent application No. 63-155720.
It was also proposed that Si or B ion be previously implanted into not only source/drain regions but also under gate electrode side walls to make the surface of the silicon substrate amorphous to suppress channeling from appealing in the subsequent ion-implantation of B or BF.sub.2 to form p-type diffusion layers. This technique is disclosed, for example, the Japanese laid-open patent application No. 4-158529.
The above techniques have the following problems. As the gate length is required to be reduced to 0.2 micrometers or less, the junction depth of the diffusion layers is required to be reduced to 0.15 micrometer or less. Actually, however, there is another problem with difficulty to form contacts on such extremely shallow diffusion layers due to penetration of contact metals through the shallow diffusion layers which leads to increase. both in contact resistance and in leakage of current. There is raised still another problem with increased resistance of the diffusion layers which leads to a drop of the ON-current. There is raised yet another problem with a difficulty to form silicide layers over the source/drain diffusion layers for the purpose of reduction in resistance of the source/drain diffusion layers. In order to form silicide layers having a sufficiently reduced resistance, it is required that a refractory metal layer, be formed over source/drain diffusion silicon layers for subsequent reaction of refractory metal with silicon. The silicidation reaction makes the source/drain diffusion layers thin. If the source/drain diffusion silicon layers are extremely shallow, the silicidation reaction makes the source/drain diffusion layers extremely thin which causes increased junction resistance of the silicide layer with the source/drain diffusion layers. It is difficult to form the silicide layers of a uniform and reduced thickness with a reduced resistance.
To settle the above problem, it was proposed to form shallow diffusion layers extending under gate electrode side walls and adjacent to source and drain diffusion regions relatively deep. This is disclosed in the Japanese laid-open patent application No. 62-176166 and a device structure is illustrated in FIG. 1. Source and drain diffusion layers 30 have extending shallow diffusion layers 29 positioned under side walls 26 of a gate electrode 24.
The above third conventional technique also has different problems. Since the shallow diffusion layers are formed by ion-implantation of p-type impurity, there is a limitation to make the diffusion layers as shallow as required above when the thickness of the shallow diffusion layers is required to be about 0.1 micrometers or less.
In the above circumstances, it is required to develop a quite novel and improved method of forming shallow diffusion layers positioned under the gate side walls to make the above transistor free from the above problems and from the problems with the short channel effects described above.